1. Technical Field
The present invention relates to a semiconductor device and a method for manufacturing thereof, and particularly relates to a semiconductor device, which comprises an interconnect containing a copper-containing metal and a method for manufacturing thereof.
2. Related Art
In recent years, requirements in increasing operation speed of semiconductor devices promotes application of lower resistive materials such as copper and the like for interconnect materials. When a copper-containing metal is employed for an interconnect material, a barrier insulating film for preventing a diffusion of copper (Cu) is provided in a lower layer of an insulating interlayer.
Meanwhile, as the level of the miniaturization of the semiconductor device is progressed, a signal delay due to an increased parasitic capacitance between interconnects is more considerably exhibited, and thus an improvement thereof is expected. To solve the problem, a low dielectric constant film (low-k film) is employed for an insulating interlayer. In addition, a reduced dielectric constant is also required for the above described barrier insulating film.
However, a reduced dielectric constant of the barrier insulating film leads to a decrease of film density of the barrier insulating film. Since a decrease of film density leads to a deterioration of a resistance to oxidization of copper, the surface of the copper interconnect is easily oxidized. There is a concern that this configuration provides a decrease of reliability including an electromigration (EM), a stress induced voiding (SIV) or a time-dependent dielectric breakdown (TDDB) of oxide film.
Typical conventional technologies concerning surface treatment of copper interconnect are described in U.S. Pat. No. 6,146,988, U.S. Pat. No. 6,599,827, Japanese Patent Laid-Open No. 2002-246,391 and Gosset, Laurent G., et al., entitled “Integration And Characterization of A Self-Aligned Barrier to Cu Diffusion Based on Copper Silicide” Conference Proceedings AMC XIX, pp. 321-328, 2004.
U.S. Pat. No. 6,146,988 discloses exposing a surface of a copper interconnect to ammonia plasma.
U.S. Pat. No. 6,599,827 discloses conducting an ammonia plasma-processing and a silane gas processing after a copper interconnect is formed.
Japanese Patent Laid-Open No. 2002-246,391 discloses treating a copper interconnect within a gaseous mixture containing silane gas and ammonia gas under a condition for generating a plasma.
Further, Gosset, Laurent G., et al., entitled “Integration And Characterization of A Self-Aligned Barrier to Cu Diffusion Based on Copper Silicide” Conference Proceedings AMC XIX, pp. 321-328, 2004, discloses conducting a combined processing of an ammonia plasma processing and a silane exposure processing for a copper interconnect.